AArch64 MP+dmb.sy+pos-[fr-rf]-addr-rfi-ctrlisb
"DMB.SYdWW Rfe PosRR FrLeave RfBack DpAddrdW Rfi DpCtrlIsbdR Fre"
Cycle=Rfi DpCtrlIsbdR Fre DMB.SYdWW Rfe PosRR FrLeave RfBack DpAddrdW
Relax=
Safe=Rfi Rfe Fre PosRR DMB.SYdWW DpAddrdW DpCtrlIsbdR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe PosRR FrLeave RfBack DpAddrdW Rfi DpCtrlIsbdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X6=z; 1:X9=x;
2:X1=y;
}
P0 | P1 | P2 ;
MOV W0,#1 | LDR W0,[X1] | MOV W0,#2 ;
STR W0,[X1] | LDR W2,[X1] | STR W0,[X1] ;
DMB SY | LDR W3,[X1] | ;
MOV W2,#1 | EOR W4,W3,W3 | ;
STR W2,[X3] | MOV W5,#1 | ;
| STR W5,[X6,W4,SXTW] | ;
| LDR W7,[X6] | ;
| CBNZ W7,LC00 | ;
| LC00: | ;
| ISB | ;
| LDR W8,[X9] | ;
Observed
z=1; y=1; x=1; 1:X8=1; 1:X7=1; 1:X3=1; 1:X2=0; 1:X0=1;